A storage subsystem is an apparatus for providing a data storage service to a host apparatus. A storage system is configured by a host apparatus being connected to a storage subsystem. A storage subsystem comprises a disk array device configured from a plurality of hard disk drives as memory devices, and a controller for controlling the input and output of data between the host apparatus and the disk array device.
The controller comprises a processor for controlling the overall storage subsystem, a host interface to the host apparatus, and a disk interface to the disk array device, and a cache memory for caching user data is arranged between both interfaces.
This kind of storage subsystem is described, for example, in Japanese Patent Laid-Open Publication No. 2009-9200. This storage subsystem has a structure where a controller including a plurality of processors is connected to a host interface, a disk interface, and a cache memory with a switch LSI.
In this storage system, if a failure occurs in any one of the components in the controller, the I/O path of the controller is cut off, and a component that failed in this cutoff status is identified and disabled. After the failed component is disabled, whether the intended processing can be performed with only the normal components is determined, and, if it is determined that this is possible, the cutoff of the I/O path is cancelled (released), and the operation is resumed after restart.
Moreover, Japanese Patent Laid-Open Publication No. 2007-207007 describes a storage system comprising a disk drive and a storage controller. The storage controller comprises one or more interfaces to be connected to a host computer, and a plurality of processors to be connected to the interfaces. The processors provide one or more logical access ports to the host computer, and the interfaces store routing information showing the processing to process the access request addressed to the logical access port. If an interface receives an access request from the host computer, it extracts an address from the received access request and, based on the routing information and the extracted address, identifies the processor to process the received access request, and transfers the received access request to the identified processor.
In addition, U.S. Pat. No. 7,421,532 describes a method for realizing a multirate structure with address mapping based on a switch LSI.